Digital Verification Engineer - Sicilia, Italia - Confidenziale
Descrizione
Digital Verification Engineer - Thesis M/F Posting title Digital Verification Engineer - Thesis M/F Regular/Temporary Temporary Contract duration (nb of months) 6 We are looking for students who are curious to discover the Digital Functional Verification techniques which allow to grant best quality to our STM32 Microcontrollers.
You will discover how to find bugs in a Digital Design, how to simulate a functional behavior and the STM32 microarchitecture.
You will work in a team, contributeto develop uVM components to verify Digital IPs and implement formal assertions to prove the correctness of the design implementation, with advanced methodologies and tools.
198/2006 which guarantees gender equality at work Job location Less than 2 years Requester 01/11/2021 General information Reference Job level 30 - Graduate Entry Level You may be interested in these vacancies
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