Analog Design Engr - Pavia, Italia - Synopsys

Synopsys
Synopsys
Azienda verificata
Pavia, Italia

3 settimane fa

Piero Bianchi

Inviato da:

Piero Bianchi

Reclutatore di talenti per beBee
Descrizione
42561BR

  • ITALY
  • Pavia

Job Description and Requirements

  • We're looking for an
-
Analog Design Engineer to join our team. Does this sound like a good role for you?

  • In this role, you will work on the design, development, and refinement of Multi-Gbps PAM4 SERDES IP. You will be part of a fastgrowing analog and mixed signal R&D team, developing high speed analog integrated circuits in the latest FinFET process nodes. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, inhouse tools supported by an experienced software/CAD team. Job Responsibilities
  • Investigate and contribute developing circuit architectures that address architectural bottlenecks and drive to revolutionary improvements in power, area and performance targets.
  • Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
  • Document design features and test plans.
  • Consult on the overall electrical characterization of the SerDes IP product. Investigate customer silicon data for design enhancements. Propose solutions for postsilicon design updates.
Job Requirements

  • PhD, or MSc with 2+ years of practical analog IC design experience. Degree in Electrical Engineering or similar.
  • Understanding of transistor level circuit design sound CMOS design fundamentals.
  • Design experience with at least one subcircuit relevant to SerDes: receive equalizers, samplers, voltage/currentmode drivers, serializers, deserializers, voltagecontrolled oscillator, phase mixer, delaylocked loop, phase locked loop, bandgap reference, ADC, DAC
Experience in the following aspects of the design process is considered as a plus:

  • Understanding of layout effects (i.e. matching, reliability, proximity effects, etc.).
  • Knowledgeable in Verilog-A for analog behavioral modeling
  • Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is a nice to have.
  • At Synopsys, we're at the heart of the innovations that change the way we work and play. Selfdriving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability._

Job Category

  • Engineering

Country

  • Italy

Job Subcategory

  • Analog Design

Hire Type

  • Employee
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