Digital Verification Engineer M/F - Catania, Italia - ST Microelectronics

Descrizione

Company department: Digital Verification Engineer
At STMicroelectronics, we are 50,000+ creators and makers of semiconductor technologies. We are a global business that prides itself on diversity nationalities and present in 35 countries.
Our people are at the heart of everything we do, working with customers and partners to create the innovations that enable the technology of tomorrow. Working at ST means innovating for a future that we want to make smarter, greener, and more sustainable. And doing this in a responsible and sustainable way.
Our technology starts with you. Join us and start the future

POSTING PRESENTATION:

To be part of a consolidated team which main purpose is to develop and implement a digital verification environment which aims is to demonstrated that the functional behavior of a provided digital block is in line with the expected description reported in the specification.
In particular this gives the opportunity to work on the:

• verification strategy definition and the verification plan, based on the Digital IP specification and microarchitecture and including the coverage model;
• verification environment development, the test suite running, debugging and bug reporting;
• coverage analysis and project closure, including the final verification document and the project review.

The environment will be created and implemented taking care of the today widely spread state of the art of the verification methodology (UVM) together with the best tools provided by our CAD vendor to reach the final target.
The implementation of the verification environment allows the possibility to interact with other relevant part of the digital flow, as well as analog part for some mixed required verification.
It's a great opportunity to get a more exhaustive view of the digital design development flow (from the beginning up to the end) being part of a well consolidated and expert team.

PROFILE REQUIRED:

Technical competences include:

• Constrained-driven verification, UVM methodology and System Verilog Language or Object Oriented languages
• Formal verification methodologies and SVA;
• Python and TCL/TK scripting languages, object oriented programming languages;
• HDL (VHDL/Verilog) languages;
• Main EDA verification tools platforms for both simulation and formal verification;

The Employment search is addressed to candidates of both genders, under Law n. 125, as amended by Legislative Decree n. 198/2006 which guarantees gender equality at work
Experience level required
2-5 years

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